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XC2C64 CoolRunner-II CPLD
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DS092 (v1.0) December 19, 2001
Advance Product Specification
Features
* Industries best 0.18 micron CMOS CPLD - 4.0 ns pin-to-pin logic delays - less than 100 A standby current consumption - 64 macrocells with up to 1,600 logic gates - Fast input registers - Slew rate control on individual outputs - LVCMOS 1.8V through 3.3V - LVTTL 3.3V Available in multiple package styles - 44-pin PLCC with 33 user I/O - 44-pin VQFP with 33 user I/O - 56-ball CP (0.05mm) BGA with 45 user I/O - 100-pin VQFP with 64 user I/O Optimized for high performance 1.8V systems - Ultra low power operation - Advanced 0.18 micron 4-metal layer Non-volatile process Advanced system features - Quadruple enhanced security - Multi-voltage system interface - Hot pluggable - IEEE1532 In-system programmable - Superior pin locking through PLA array - Input hysteresis (Schmitt trigger) on all pins - Bus hold circuitry on all user pins - IEEE standard 1149.1 boundary scan (JTAG) - Fast programming times - Excellent pin retention during design changes - High quality and reliability - Guaranteed 10,000 program/erase cycles - 20 year data retention
Description
The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and speed to battery operated devices. This device consists of four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 inputs to each Function Block. The Function Blocks consist of a 40 by 56 p-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term based, on a per macrocell basis. Output control signals include slew rate control, bus hold and open drain. An additional Schmitt-trigger input is available on a per input pin basis. In addition to combinatorial and registered outputs, the registers may be configured as fast inputs. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Global clocks are additionally used to set or preset individual macrocell registers on power up. Local clocks are generated in specific Function Blocks and only available to macrocell registers in that Function Block. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows performance where it is needed without raising the total power consumption of the entire device. The CoolRunner-II 64-macrocell CPLD is I/O compatible with standard LVTTL33 and LVCMOS18, 25, and 33 volts (see Table 1).
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Refer to the CoolRunnerTM-II family data sheet for architecture description.
Fast Zero Power Design Technology
All CoolRunner-II CPLDs employ Fast Zero PowerTM (FZP), a design technique that employs CMOS technology in both the fabrication and design methodology. Xilinx CoolRunner-II is fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this FZP technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation.
(c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS092 (v1.0) December 19, 2001 Advance Product Specification
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XC2C64 CoolRunner-II CPLD
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Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JESDSA standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V, and 1.5V applications. It does not require the use of a reference voltage or termination voltage. Table 1: I/O Standards for XC2C64 I/O Standard LVTTL LVCMOS33 LVCMOS25 LVCMOS18 Output VCCIO 3.3V 3.3 2.5 1.8 Input VCCIO 3.3V 3.3 2.5 1.8 Input VREF N/A N/A N/A N/A Board Termination Voltage VT N/A N/A N/A N/A
25
20
ICC (mA)
15
10
5
0 0 50 100 150 200 250 300
Frequency (MHz)
DS092_07_121501
Figure 1: ICC vs Frequency
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C) Frequency (MHz) 50 Typical ICC (mA) 3.6 75 5.5 100 7.3 125 9.1 150 10.8 175 12.5 200 14.2 225 15.9 250 17.5 275 19.2 300 20.8
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DS092 (v1.0) December 19, 2001 Advance Product Specification
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XC2C64 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol VCC VCCIO VIN VTS VSTG TSOL TJ Description Supply voltage relative to ground Supply voltage for output drivers Input voltage relative to ground(1) Voltage applied to 3-state output(1) Value -0.5 to 2.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -65 to +150 + 60 + 50 Units V V V V C C C
Storage Temperature (ambient) Maximum Soldering temperature (10s @ 1/16in. = 1.5mm) Junction Temperature
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to -2.0v or overshoot to +3.9V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Recommended Operating Conditions
Symbol VCC VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0C to +70C Industrial TA = -40C to +85C Min 1.7 1.7 3.0 2.3 1.7 1.4 Max 1.9 1.9 3.6 2.7 1.9 1.6 Units V V V V V V
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation(1)
Notes: 1. Use input hysteresis for 1.5V LVCMOS.
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol VCCIO VIH VIL VOH VOL IIL IIH ICCSB ICC CJTAG CCLK CIO Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level input voltage Input leakage current I/O High-Z leakage Standby current Dynamic current JTAG input capacitance Global clock input capacitance I/O capacitance IOH = -8 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V VIN = 0 or VCCIO VIN = 0 or VCCIO VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz Test Conditions Min. 3.0 2.0 -0.3 2.4 -10 -10 Max. 3.6 VCCIO+ 0.3V 0.8 0.4 10 10 100 Units V V V V V A A A mA mA pF pF pF
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LVCMOS 3.3V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V VOL Low level input voltage IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V IIL IIH CJTAG CCLK CIO Input leakage current I/O High-Z leakage JTAG input capacitance Global clock input capacitance I/O capacitance VIN = 0V or VCCIO VIN = 0V or VCCIO f = 1 MHz f = 1 MHz f = 1 MHz Test Conditions Min. 3.0 2 -0.3 VCCIO - 0.4V VCCIO - 0.2V -10 -10 Max. 3.6 VCCIO + 0.3V 0.8 0.4 0.2 10 10 Units V V V V V V V A A pF pF pF
LVCMOS 2.5V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V VOL Low level output voltage IOL = 8 mA, VCCIO = 3V IOL = 0.1mA, VCCIO = 3V IIL IIH CJTAG CCLK CIO Input leakage current I/O High-Z leakage JTAG input capacitance Global clock input capacitance I/O capacitance VIN = 0V or VCCIO VIN = 0V or VCCIO to 3.9V f = 1 MHz f = 1 MHz f = 1 MHz Test Conditions Min. 2.3 1.7 -0.3 VCCIO - 0.4V VCCIO - 0.2V -10 -10 Max. 2.7 3.9 0.7 0.4 0.2 10 10 Units V V V V V V V V V pF pF pF
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DS092 (v1.0) December 19, 2001 Advance Product Specification
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XC2C64 CoolRunner-II CPLD
LVCMOS 1.8V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V VOL Low level input voltage IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V IIL IIH CJTAG CCLK CIO Input leakage current I/O High-Z leakage JTAG input capacitance Global clock input capacitance I/O capacitance VIN = 0 or VCCIO to 3.9V VIN = 0 or VCCIO to 3.9V f = 1 MHz f = 1 MHz f = 1 MHz Test Conditions Min. 1.7 0.7 x VCCIO -0.3 VCCIO -0.45 VCCIO -0.2 -10 -10 Max. 1.9 3.9 0.2 x VCCIO 0.45? 0.2 10 10 Units V V V V V V V A A pF pF pF
1.5V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V VOL Low level input voltage IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V IIL IIH CJTAG CCLK CIO Input leakage current I/O High-Z leakage JTAG input capacitance Global clock input capacitance I/O capacitance VIN = 0 or VCCIO to 3.9V VIN = 0 or VCCIO to 3.9V f = 1 MHz f = 1 MHz f = 1 MHz -10 -10 Test Conditions Min. 1.4 0.7 x VCCIO -0.3 VCCIO - 0.45 VCCIO - 0.2 0.4 0.2 10 10 Max. 1.6 3.9 0.3 Units V V V V V V V A A pF pF pF
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AC Electrical Characteristics Over Recommended Operating Conditions
-4 Symbol TPD1 TPD2 TSU1 TSU2 TH1 TH2 TCO TTOGGLE FSYSTEM FEXT TPSU1 TPSU2 TPH1 TPH2 TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC1 TSUEC2 THEC1 THEC2 TCW TPCW TCONFIG Parameter Propagation delay single p-term Propagation delay OR array Setup time fast Setup time Fast input register hold time P-term hold time Clock to output Internal toggle rate Maximum system frequency Maximum external frequency Fast input register p-term clock setup time P-term clock setup time Fast input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Fast input register clock enable setup time Register clock enable setup time Fast input register clock enable hold time Register clock enable hold time Global clock pulse width High or Low P-term pulse width High or Low Configuration time Min. 1.6 2.0 0 0 1.0 1.4 0.4 0.3 1.6 2.0 0 0 1.2 4.0 Max. 3.7 4.0 3.0 416 270 200 3.6 3.9 4.3 4.9 5.4 5.5 Min. 1.9 2.4 0 0 1.2 1.7 0.6 0.5 1.9 2.4 0 0 2.0 5.0 -5 Max. 4.6 5.0 3.9 250 213 159 4.6 4.9 5.3 6.3 6.4 6.5 Min. 2.3 3.3 0 0 1.5 2.5 0.7 0.5 2.3 3.3 0 0 3.0 7.5 -7 Max. 6.7 7.5 6.0 168 141 108 6.8 7.0 7.3 9.2 9.1 9.3 Units ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us
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DS092 (v1.0) December 19, 2001 Advance Product Specification
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XC2C64 CoolRunner-II CPLD
Internal Timing Parameters
-4 Symbol
Buffer Delays
-5 Max. Min. Max. Min.
-7 Max. Units
Parameter(1)
Min.
TIN TFIN TGCK TGSR TGTS TOUT TEN
P-term Delays
Input buffer delay Fast data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay
-
1.3 1.6 1.2 1.9 1.4 1.6 2.5
-
1.7 2.1 1.6 2.4 1.9 1.9 3.0
-
2.4 3.0 2.5 3.5 3.0 2.8 4.0
ns ns ns ns ns ns ns
TCT TLOGI1 TLOGI2 TPDI TSUI THI TECSU TECHO TCOI TAOI TCDBL TF TOEM TIN15 THYS15 TOUT15 TSLEW15 TIN18 THYS18 TOUT18 TSLEW
Control term delay Single P-term delay adder Multiple P-term delay adder
-
0.5 0.4 0.3
-
0.6 0.5 0.4
-
0.9 0.8 0.8
ns ns ns
Macrocell Delay
Input to output valid Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid Clock doubler delay
1.2 0 1.2 0 -
0.4 0.2 2.0 0
1.4 0 1.4 0 -
0.5 0.4 2.2 0
1.8 0 1.8 0 -
0.7 0.7 3.0 0
ns ns ns ns ns ns ns ns
Feedback Delays
Feedback delay Macrocell to global OE delay
-
1.6 1.0
-
2.0 1.3
-
3.0 2.0
ns ns
I/O Standard Time Adder Delays 1.5V CMOS
Standard input adder Hysteresis input adder Output adder Output slew rate adder
ns ns ns ns
I/O Standard Time Adder Delays 1.8V CMOS
Standard input adder Hysteresis input adder Output adder Output slew rate adder
-
0 2.0 0 2.0
-
0 3.0 0 3.0
-
0 4.0 0 4.0
ns ns ns ns
I/O Standard Time Adder Delays 2.5V CMOS
DS092 (v1.0) December 19, 2001 Advance Product Specification
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Internal Timing Parameters (Continued)
-4 Symbol TIN25 THYS25 TOUT25 TSLEW25 TIN33 THYS33 TOUT33 TSLEW33 Parameter(1) Standard input adder Hysteresis input adder Output adder Output slew rate adder Min. Max. 0.5 1.5 1.5 2.0 Min. -5 Max. 0.8 2.5 2.5 3.0 Min. -7 Max. 1.0 3.0 3.0 4.0 Units ns ns ns ns
I/O Standard Time Adder Delays 3.3V CMOS/TTL
Standard input adder Hysteresis input adder Output adder Output slew rate adder
-
0.7 1.0 1.0 2.0
-
1.0 2.0 2.0 3.0
-
2.0 3.0 3.0 4.0
ns ns ns ns
Notes: 1. 1.5 ns input pin signal rise/fall.
Switching Characteristics
VCC = 1.8V, 25oC
6.0
5.8
TPD_PAL (ns)
5.6
4.4
4.2
4.0 12 4 8 12 16
Number of Outputs Switching
DS092_09_121501
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DS092 (v1.0) December 19, 2001 Advance Product Specification
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XC2C64 CoolRunner-II CPLD
Pin Descriptions
Function Block 1 1 1 1 1 1 1 1 1(GTS1) 1(GTS0) 1(GTS3) 1(GTS2) 1(GRS) 1 1 1 2 2 2 2 2 2 2(GCK0) 2(GCK1) 2 2(GCK2) 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PC44 44 43 42 40 39 38 37 36 1 2 3 4 5 6 7 8 9 VQ44 38 37 36 34 33 32 31 30 39 40 41 42 43 44 1 2 3 CP56 F1 E3 E1 D3 D1 C1 A3 A2 B1 A1 C3 A4 G1 F3 H1 G3 J1 K1 K4 K2 K3 H3 K5 VQ100 13 12 11 10 9 8 7 6 4 3 2 1 99 97 94 92 14 15 16 17 18 19 22 23 24 27 28 29 30 32 33 34
Pin Descriptions (Continued)
Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PC44 35 34 33 29 28 27 26 25 24 11 12 14 18 19 20 22 VQ44 29 28 27 23 22 21 20 19 18 5 6 8 12 13 14 16 CP56 C4 A4 C5 A7 C8 A8 A9 A5 A10 B10 C10 D8 E8 D10 K6 H5 H7 H8 K8 H10 G10 F10 E10 VQ100 91 90 89 81 79 78 77 76 74 72 71 70 68 67 64 61 35 36 37 39 40 41 42 43 49 50 52 53 55 56 58 60
Note: GTS = global output enable, GRS = global reset/set, GCK = global clock x
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XC2C64 CoolRunner-II CPLD
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XC2C64 Global, JTAG, Power/Ground and No Connect Pins
Pin Type TCK TDI TDO TMS VAUX (JTAG supply voltage) Power internal (VCC) Power external I/O (VCCIO) Ground No connects Total user I/O 33 33 45 PC44 17 15 30 16 41 21 13, 32 10,23,31 VQ44 11 9 24 10 35 15 7,26 4,17,25 CP56 K10 J10 A6 K9 D3 G8 H6, C6 H4, F8, C7 VQ100 48 45 83 47 5 26,57 38, 51,88, 98 21,31,62,69,84,100 20,25,44,46,54,59,63,65,66,73,75, 80,82,85,86,87,93,95,96 64
Ordering Information
Part Number XC2C64-4PC44C XC2C64-5PC44C XC2C64-7PC44C XC2C64-4VQ44C XC2C64-5VQ44C XC2C64-7VQ44C XC2C64-4CP56C XC2C64-5CP56C XC2C64-7CP56C XC2C64-4VQ100C XC2C64-5VQ100C XC2C64-7VQ100C XC2C64-5PC44I XC2C64-7PC44I XC2C64-5VQ44I XC2C64-7VQ44I XC2C64-5CP56I XC2C64-7CP56I XC2C64-5VQ100I XC2C64-7VQ100I Pin/Ball Spacing 1.27mm 1.27mm 1.27mm 0.8mm 0.8mm 0.8mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.8mm 1.27mm 1.27mm 0.8mm 0.8mm 0.5mm 0.5mm 0.5mm 0.5mm JA (C/Watt) 53.1 53.1 53.1 46.6 46.6 46.6 65.0 65.0 65.0 53.2 53.2 53.2 53.1 53.1 46.6 46.6 65.0 65.0 53.2 53.2 JC (C/Watt) 28.7 28.7 28.7 8.2 8.2 8.2 15.0 15.0 15.0 14.6 14.6 14.6 28.7 28.7 8.2 8.2 15.0 15.0 14.6 14.6 Commercial (C) Package Type Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Very Thin Quad Flat Pack Very Thin Quad Flat Pack Very Thin Quad Flat Pack Chip Scale Package Chip Scale Package Chip Scale Package Very Thin Quad Flat Pack Very Thin Quad Flat Pack Very Thin Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Very Thin Quad Flat Pack Very Thin Quad Flat Pack Chip Scale Package Chip Scale Package Very Thin Quad Flat Pack Very Thin Quad Flat Pack I/O 33 33 33 33 33 33 45 45 45 64 64 64 33 33 33 33 45 45 64 64 Industrial (I) C C C C C C C C C C C C I I I I I I I I
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DS092 (v1.0) December 19, 2001 Advance Product Specification
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XC2C64 CoolRunner-II CPLD
I/O I/O I/O VAUX I/O(1) I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
I/O VCCIO I/O TDI TMS TCK I/O I/O I/O VCC I/O
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset
Figure 2: PQ44 Package
K J H G F E D C B A
I/O(2) I/O(2)
I/O(2)
I/O
I/O
I/O
I/O
I/O
I/O
TMS
TCK
TDI
I/O
I/O
GND
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
CP56 Bottom View
GND
I/O
I/O I/O(1) I/O(1) I/O(3) I/O(1)
I/O
I/O
I/O
VAUX I/O I/O I/O VCCIO GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO
I/O
I/O
I/O
I/O
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset
Figure 4: CP56 Package
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10
1
2
3
4
5
6
7
8
9
I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O
12 13 14 15 16 17 18 19 20 21 22
I/O I/O I/O I/O I/O(2) I/O(2) I/O(2) I/O I/O GND I/O
1 2 3 4 5 6 7 8 9 10 11
PQ44 Top View
33 32 31 30 29 28 27 26 25 24 23
I/O VCCIO Gnd TDO I/O I/O I/O I/O I/O I/O GND
44 43 42 41 40 39 38 37 36 35 34
I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O I/O VAUX I/O(1)
I/O(2) I/O I/O GND I/O I/O VCCIO I/O TDI TMS TCK
1 2 3 4 5 6 7 8 9 10 11
VQ44 Top View
33 32 31 30 29 28 27 26 25 24 23
I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O I/O VCCIO GND TDO I/O
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset
Figure 3: VQ44 Package
XC2C64 CoolRunner-II CPLD
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND I/O(3) VCCIO I/O NC NC I/O NC I/O I/O I/O I/O VCCIO NC NC NC GND TDO NC I/O NC I/O I/O I/O I/O
I/O(1) I/O(1) I/O(1) I/O(1) VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND I/O(2) I/O(2) I/O NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VQ100 Top View
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset
Revision History
The following table shows the revision history for this document. Date 12/19/01 Version 0.1 Initial final draft. Revision
12
VCC I/O(2) I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O NC TDI NC TMS TCK I/O I/O
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC I/O NC I/O I/O I/O GND I/O I/O NC NC I/O NC GND I/O I/O NC I/O Vcc I/O I/O NC I/O I/O VCCIO
Figure 5: VQ100 Package
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